diff --git a/examples/hello.s b/examples/hello.s
new file mode 100644
index 0000000..ef32317
--- /dev/null
+++ b/examples/hello.s
@@ -0,0 +1,18 @@
+.data:
+text0 "Hello, World!\n"
+file_name "example.txt"
+.code:
+sd.int32 $4 123
+write_file:
+sd.int32 $20 -4
+sd.int32 $10 file_name
+sd.int32 $11 11
+sd.int32 $12 1
+sys 5
+sd.int32 $11 text0
+sd.int32 $12 14
+sys 4
+return
+sd.int32 $10 100
+sys 1
+bmath add Int32 $4 $5 $6
diff --git a/src/SVM.Assembler/ISA.xml b/src/SVM.Assembler/ISA.xml
index 66ec493..8a952ca 100644
--- a/src/SVM.Assembler/ISA.xml
+++ b/src/SVM.Assembler/ISA.xml
@@ -130,6 +130,7 @@
 		<InstructionDefinition Id="return" PrimaryInstruction="Return" InstructionCount="1">
 			<Aliases>
 				<Alias Name="return"/>
+				<Alias Name="ret"/>
 			</Aliases>
 			<Parameters>
 				<InstructionParameter>
diff --git a/src/SVM.Core/PrimaryInstruction.cs b/src/SVM.Core/PrimaryInstruction.cs
index fb0aeee..fd04881 100644
--- a/src/SVM.Core/PrimaryInstruction.cs
+++ b/src/SVM.Core/PrimaryInstruction.cs
@@ -26,13 +26,13 @@
 		SD,
 
 		// 0	1
-		// JAL	RD
+		// JMP	RD
 		// [I]Address (int32)
-		JAL,
+		JMP,
 		// Jump And Link If Conditional Register is set.
-		// JALF RD FlagID
+		// JIF RD FlagID
 		// [I]Address (int32)
-		JALF,
+		JIF,
 		// 0	1			2		3
 		// Load [R]Address	[I]Len	[R]T
 		Load,
diff --git a/src/SVM.Core/SimpleVirtualMachine.cs b/src/SVM.Core/SimpleVirtualMachine.cs
index a357985..7ef2f66 100644
--- a/src/SVM.Core/SimpleVirtualMachine.cs
+++ b/src/SVM.Core/SimpleVirtualMachine.cs
@@ -217,9 +217,9 @@ namespace SVM.Core
 							//Console.WriteLine($"SVM:SD:{data} form PC={PC}");
 						}
 						break;
-					case PrimaryInstruction.JAL:
+					case PrimaryInstruction.JMP:
 						break;
-					case PrimaryInstruction.JALF:
+					case PrimaryInstruction.JIF:
 						break;
 					case PrimaryInstruction.Load:
 						{