diff --git a/src/SVM.Assembler.Core/Assembler.cs b/src/SVM.Assembler.Core/Assembler.cs
index d8be97c..6bef04f 100644
--- a/src/SVM.Assembler.Core/Assembler.cs
+++ b/src/SVM.Assembler.Core/Assembler.cs
@@ -14,15 +14,6 @@ namespace SVM.Assembler.Core
 @"
 Match:
 
-InstMath bmath
-InstSDInt32 sd\.int32
-InstSDInt sd\.int
-InstSDInt64 sd\.int64
-InstSDLong sd\.long
-InstCvt cvt
-InstSystem system
-InstSys sys
-InstSD sd
 Register \${D}+
 LabelCode \.code\:
 LabelData \.data\:
@@ -37,15 +28,6 @@ D \d
 
 Id:
 word Word
-InstSDInt64 inst
-InstSDLong inst
-InstMath inst
-InstSDInt inst
-InstSDInt32 inst
-InstCvt inst
-InstSystem inst
-InstSys inst
-InstSD sd
 string String
 Number Number
 Register Register
diff --git a/src/SVM.Assembler/ISA.xml b/src/SVM.Assembler/ISA.xml
index ee37af4..e4fdcc6 100644
--- a/src/SVM.Assembler/ISA.xml
+++ b/src/SVM.Assembler/ISA.xml
@@ -140,5 +140,34 @@
 				</InstructionParameter>
 			</Parameters>
 		</InstructionDefinition>
+		<InstructionDefinition Id="save" PrimaryInstruction="Save" InstructionCount="1">
+			<Aliases>
+				<Alias Name="save"/>
+				<Alias Name="sd"/>
+			</Aliases>
+			<Parameters>
+				<InstructionParameter>
+					<MatchingItems>
+						<Item Id="Register"/>
+						<Item Id="Word"/>
+					</MatchingItems>
+					<ExpectedValue Type="UInt8" Pos="1" Converter="Register" />
+				</InstructionParameter>
+				<InstructionParameter>
+					<MatchingItems>
+						<Item Id="Number"/>
+						<Item Id="Word"/>
+					</MatchingItems>
+					<ExpectedValue Type="UInt8" Pos="2" Converter="UInt8" />
+				</InstructionParameter>
+				<InstructionParameter>
+					<MatchingItems>
+						<Item Id="Register"/>
+						<Item Id="Word"/>
+					</MatchingItems>
+					<ExpectedValue Type="UInt8" Pos="3" Converter="Register" />
+				</InstructionParameter>
+			</Parameters>
+		</InstructionDefinition>
 	</Definitions>
 </ISARoot>
\ No newline at end of file